• DocumentCode
    981802
  • Title

    Array architectures for iterative algorithms

  • Author

    Jagadish, Hosagrahar V. ; Rao, Sailesh K. ; Kailath, Thomas

  • Author_Institution
    AT&T Bell Laboratories, Murray Hill, NJ, USA
  • Volume
    75
  • Issue
    9
  • fYear
    1987
  • Firstpage
    1304
  • Lastpage
    1321
  • Abstract
    Regular mesh-connected arrays are shown to be isomorphic to a class of so-called regular iterative algorithms. For a wide variety of problems it is shown how to obtain appropriate iterative algorithms and then how to translate these algorithms into arrays in a systematic fashion. Several "systolic" arrays presented in the literature are shown to be specific cases of the variety of architectures that can be derived by the techniques presented here. These include arrays for Fourier Transform, Matrix Multiplication, and Sorting.
  • Keywords
    Computer architecture; Costs; Fourier transforms; Hardware; Iterative algorithms; Laboratories; Missiles; Sorting; Systolic arrays; USA Councils;
  • fLanguage
    English
  • Journal_Title
    Proceedings of the IEEE
  • Publisher
    ieee
  • ISSN
    0018-9219
  • Type

    jour

  • DOI
    10.1109/PROC.1987.13882
  • Filename
    1458149