DocumentCode :
9835
Title :
High-Performance Implementation of Point Multiplication on Koblitz Curves
Author :
Azarderakhsh, Reza ; Reyhani-Masoleh, Arash
Author_Institution :
Dept. of Combinatorics & Optimization, Univ. of Waterloo, Waterloo, ON, Canada
Volume :
60
Issue :
1
fYear :
2013
fDate :
Jan. 2013
Firstpage :
41
Lastpage :
45
Abstract :
Fast and high-performance computation of finite-field arithmetic is crucial for elliptic curve cryptography (ECC) over binary extension fields. In this brief, we propose a highly parallel scheme to speed up the point multiplication for high-speed hardware implementation of ECC cryptoprocessor on Koblitz curves. We slightly modify the addition formulation in order to employ four parallel finite-field multipliers in the data flow. This reduces the latency of performing point addition and speeds up the overall point multiplication. To the best of our knowledge, the proposed data flow of point addition has the lowest latency in comparison to the counterparts available in the literature. To make the cryptoprocessor more efficient, we employ a low-complexity and efficient digit-level Gaussian normal basis multiplier to perform lower level finite-field multiplications. Finally, we have implemented our proposed architecture for point multiplication on an Altera Stratix II field-programmable gate array and obtained the results of timing and area.
Keywords :
field programmable gate arrays; public key cryptography; Altera Stratix II field-programmable gate array; ECC cryptoprocessor; Koblitz curves; binary extension field; cryptoprocessor; digit-level Gaussian normal basis multiplier; elliptic curve cryptography; finite field arithmetic; finite-field multiplications; high-performance implementation; high-speed hardware implementation; parallel finite-field multipliers; point multiplication; Clocks; Computer architecture; Elliptic curve cryptography; Elliptic curves; Field programmable gate arrays; Gaussian processes; Cryptoprocessor; Koblitz curves; elliptic curve cryptography (ECC); field-programmable gate array (FPGA); parallel processing; point multiplication;
fLanguage :
English
Journal_Title :
Circuits and Systems II: Express Briefs, IEEE Transactions on
Publisher :
ieee
ISSN :
1549-7747
Type :
jour
DOI :
10.1109/TCSII.2012.2234916
Filename :
6410400
Link To Document :
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