• DocumentCode
    984377
  • Title

    Minimum fault coverage in memory arrays: a fast algorithm and probabilistic analysis

  • Author

    Low, Chor-Ping ; Leong, Hon Wai

  • Author_Institution
    Dept. of Inf. Syst. & Comput. Sci., Nat. Univ. of Singapore, Singapore
  • Volume
    15
  • Issue
    6
  • fYear
    1996
  • fDate
    6/1/1996 12:00:00 AM
  • Firstpage
    681
  • Lastpage
    690
  • Abstract
    The problem of reconfiguring memory arrays using spare rows and spare columns is known to be NP-complete and has received a great deal of attention in recent years. For reason of cost effectiveness, it is desirable in practice to find minimum reconfiguration solutions. While numerous algorithms have been proposed to find minimum reconfiguration solutions, they all run in worst case exponential time complexities. On the other hand, existing heuristic algorithms with fast polynomial running time cannot guarantee minimum solutions. This paper presents a provably good heuristic algorithm for finding minimum reconfiguration solution. Using random bipartite graphs, we prove that the reconfiguration problem is almost always optimally solvable with our new algorithm in polynomial time for all practical purposes. We also show that our algorithm can be used to estimate the number of spare rows and columns that are required to achieve a given percentage of yield for RRAM´s with known defect probabilities
  • Keywords
    cellular arrays; computational complexity; fault diagnosis; probability; random-access storage; redundancy; NP-complete problem; RRAMs; cost effectiveness; defect probabilities; heuristic algorithms; memory arrays; minimum fault coverage; minimum reconfiguration solutions; polynomial time; probabilistic analysis; random bipartite graphs; redundant RAM; spare columns; spare rows; Algorithm design and analysis; Bipartite graph; Circuit faults; Costs; Helium; Heuristic algorithms; Integrated circuit yield; Polynomials; Random access memory; Yield estimation;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/43.503937
  • Filename
    503937