• DocumentCode
    984440
  • Title

    EBOARST: An Efficient Edge-Based Obstacle-Avoiding Rectilinear Steiner Tree Construction Algorithm

  • Author

    Long, Jieyi ; Zhou, Hai ; Memik, Seda Ogrenci

  • Author_Institution
    Dept. of Electr. Eng. & Comput. Sci., Northwestern Univ., Evanston, IL
  • Volume
    27
  • Issue
    12
  • fYear
    2008
  • Firstpage
    2169
  • Lastpage
    2182
  • Abstract
    Obstacle-avoiding Steiner routing has arisen as a fundamental problem in the physical design of modern VLSI chips. In this paper, we present EBOARST, an efficient four-step algorithm to construct a rectilinear obstacle-avoiding Steiner tree for a given set of pins and a given set of rectilinear obstacles. Our contributions are fourfold. First, we propose a novel algorithm, which generates sparse obstacle-avoiding spanning graphs efficiently. Second, we present a fast algorithm for the minimum terminal spanning tree construction step, which dominates the running time of several existing approaches. Third, we present an edge-based heuristic, which enables us to perform both local and global refinements, leading to Steiner trees with small lengths. Finally, we discuss a refinement technique called segment translation to further enhance the quality of the trees. The time complexity of our algorithm is O(nlogn). Experimental results on various benchmarks show that our algorithm achieves 16.56 times speedup on average, while the average length of the resulting obstacle-avoiding rectilinear Steiner trees is only 0.46% larger than the best existing solution.
  • Keywords
    VLSI; integrated circuit design; network routing; trees (mathematics); EBOARST; VLSI chips; edge-based heuristic; edge-based obstacle-avoiding rectilinear Steiner tree construction; minimum terminal spanning tree construction; segment translation; sparse obstacle-avoiding spanning graphs; Algorithm design and analysis; Circuits; Electronic design automation and methodology; Pins; Routing; Steiner trees; Timing; Tree graphs; Very large scale integration; Wire; Graph algorithm; Steiner tree; obstacle-avoiding; routing;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/TCAD.2008.2006098
  • Filename
    4670065