2.5-dimensional VLSI system integration

Author

Deng, Yangdong ; Maly, Wojciech P.

Author_Institution

Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA

Volume

13

Issue

6

fYear

2005

fDate

6/1/2005 12:00:00 AM

Firstpage

668

Lastpage

677

Abstract

The excessive interconnection delay and fast increasing development cost, as well as complexity of the single-chip integration of different technologies, are likely to become the major stumbling blocks for the success of monolithic system-on-chips. To address the above problems, this paper investigates a new VLSI integration paradigm, the so-called 2.5-dimensional (2.5-D) integration scheme. Using this scheme, a VLSI system is implemented as a three-dimensional stacking of monolithic chips. A cost analysis framework was developed to justify the 2.5-D integration scheme from an economic point of view. Enabling technologies for the new integration scheme are also reviewed.

Keywords

VLSI; integrated circuit interconnections; monolithic integrated circuits; system-on-chip; 2.5D VLSI system integration; 3D stacking; interconnection delay; monolithic integrated circuits; monolithic system-on-chips; single-chip integration; CMOS technology; Costs; Delay; Fabrication; Integrated circuit interconnections; Integrated circuit technology; Monolithic integrated circuits; System-on-a-chip; Timing; Very large scale integration; 2.5-D integration; Cost; VLSI; monolithic integrated circuits;

fLanguage

English

Journal_Title

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Publisher

ieee

ISSN

1063-8210

Type

jour

DOI

10.1109/TVLSI.2005.848814

Filename

1458783