Title :
Inverted transistor gate with FET load
Author :
Saul, P.H. ; Hunt, P.C. ; Walker, R.S
Author_Institution :
Plessey Research (Caswell) Limited, Allen Clark Research Centre, Towcester, UK
Abstract :
The letter outlines preliminary results on a new logic gate for silicon bipolar VLSI. Gate delays below 4 ns have been achieved at 2 ¿W dissipation, demonstrating a power-delay product of only 8 fJ. These results are achieved on a 3 ¿m minimum feature size oxide isolated process.
Keywords :
bipolar integrated circuits; integrated logic circuits; large scale integration; logic gates; FET load; Si bipolar VLSI; gate delays; inverted transistor gate; logic gate; oxide isolated process; power dissipation; power-delay product;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19830211
