Analytical model for high-performance shallow-junction-well transistor (SJET) with a fully depleted channel structure

An analytical model for a very-shallow-junction-well transistor (SJET) is described. Solving the one-dimensional Poisson equation at the channel region, it was found that the channel depletion-layer charge can be reduced by extending the p-n junction depletion layer width between the well region and the substrate in the SJET. Therefore, in the SJET, the p-well thickness and the substrate bias are very important factors for realizing its high performance. According to this model, larger carrier mobility in the inversion layer and smaller subthreshold swing can be realized in the SJET compared to a conventional MOSFET. Moreover, by controlling the electron injection from the inversion layer to the substrate at high substrate bias, a vertical operating mode in the SJET (VSJET) can also be realized