An ultra-shallow buried-channel PMOST using boron penetration

Author

Pfiester, J.R. ; Hayden, J.D. ; Kirsch, H.C. ; Hsing-Huang Tseng ; Ravaioli, Umberto

Author_Institution

Motorola Inc., Austin, TX, USA

Volume

40

Issue

1

fYear

1993

fDate

1/1/1993 12:00:00 AM

Firstpage

207

Lastpage

213

Abstract

A novel process using controlled boron penetration to form an ultrashallow buried-layer for a sub-half-micrometer channel-length n⁺ polysilicon-gate PMOS device is presented. Experimental results coupled with two-dimensional process and device simulation are used to examine the impact of the buried-channel design on the drain-induced barrier lowering effects. Using a sacrificial 125-Å gate oxide and a BF₂-implanted polysilicon layer, the boron penetration profile is formed prior to the actual gate oxidation. This process is suitable for sub-half-micrometer channel-length n⁺ poly-gated CMOS technologies which require gate oxide thicknesses of less than 100 Å

Keywords

CMOS integrated circuits; boron; doping profiles; elemental semiconductors; insulated gate field effect transistors; integrated circuit technology; ion implantation; semiconductor doping; silicon; 0.5 micron; 100 Å; 2D process simulation; B profile; BF₂-implanted polysilicon layer; CMOS technologies; PMOS device; PMOST; Si:B; controlled B penetration; device simulation; drain-induced barrier lowering effects; gate oxidation; gate oxide thicknesses; n⁺ polysilicon-gate; polycrystalline Si:BF; ultra-shallow buried-channel; ultrashallow buried-layer; Boron; CMOS process; Degradation; Helium; MOS devices; Oxidation; Process control; Robustness; Silicon; Threshold voltage;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.249445

Filename

249445