Minimisation of on-resistance of VDMOS power FETs

The minimisation of on-resistance of power MOSFETs is a problem of considerable importance to high-voltage MOS designers. The results of a two-dimensional simulation of VDMOS structures are presented, with linear and hexagonal surface geometries, which takes account of the finite sheet resistance of the accumulation layer under the extended gate region. A simple distributed analytic model is also introduced which gives reasonable agreement with the numerical model and which may be used to give the functional relation ship of the on-resistance with device parameters.