Title :
A low-latency asynchronous shift register
Author :
Chan, Ragnarok Pak-Kee ; Choy, Oliver Chiu-Sing ; Chan, Cheong-Fat ; Pun, Kong-Pang
Author_Institution :
Dept. of Electron. Eng., Chinese Univ. of Hong Kong, China
fDate :
5/1/2004 12:00:00 AM
Abstract :
In this paper, we first introduce a straightforward asynchronous shift register design implemented by differential cascode voltage switch logic and micropipeline. The corresponding latency defect between data readout is then described. To solve this problem, we propose a new architecture for the design. Finally, a basic building block with respect to our architecture is proposed.
Keywords :
asynchronous circuits; logic design; shift registers; D flip-flop; asynchronous circuit; differential cascode voltage; low-latency register; micropipeline; shift register; switch logic; Asynchronous circuits; Circuit topology; Clocks; Delay; Flip-flops; Logic circuits; Shift registers; Switches; Switching circuits; Voltage; $D$ flip-flop; Asynchronous circuit; DCVSL; differential cascode voltage switch logic; latency; shift register;
Journal_Title :
Circuits and Systems II: Express Briefs, IEEE Transactions on
DOI :
10.1109/TCSII.2004.824051
