A delay-encoding-logic array processor for dynamic-programming matching of data sequences

Author

Ogawa, Makoto ; Shibata, Tadashi

Author_Institution

Dept. of Frontier Informatics, Univ. of Tokyo, Japan

Volume

40

Issue

7

fYear

2005

fDate

7/1/2005 12:00:00 AM

Firstpage

1578

Lastpage

1582

Abstract

Computationally very expensive dynamic-programming matching of data sequences has been directly implemented in a fully-parallel-architecture VLSI chip. The circuit operates as digital logic in the signal domain, while analog processing is carried out in the time domain based on the delay-encoding-logic scheme. As a result, a high-speed low-power best-match-sequence search has been established with a small chip area. The typical matching time of 80 ns with the power dissipation of 2 mW has been demonstrated with fabricated prototype chips.

Keywords

VLSI; delay circuits; high-speed integrated circuits; mixed analogue-digital integrated circuits; parallel architectures; programmable logic arrays; 2 mW; 80 ns; VLSI chip; analog processing; best match sequence search; data sequences matching; delay encoding logic scheme; digital logic; dynamic programming; dynamic time warping; logic array processor; parallel architecture; pattern matching; pulse-width modulation; signal domain; time-domain circuit; Computer interfaces; Delay effects; Logic arrays; Logic circuits; Pattern matching; Power dissipation; Sequences; Signal processing; Speech recognition; Very large scale integration; Analog VLSI; dynamic time warping; dynamic-programming matching; pattern matching; pulse-width modulation; sequence matching; time-domain circuit;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2005.847214

Filename

1459003