A 2.5-V 10-b 120-MSample/s CMOS pipelined ADC based on merged-capacitor switching

This work describes a 10-b multibit-per-stage pipelined CMOS analog-to-digital converter (ADC) incorporating the merged-capacitor switching (MCS) technique. The proposed MCS technique improves the signal processing speed and resolution of the ADC by reducing the required number of unit capacitors by half in comparison to a conventional ADC. The ADC resolution based on the proposed MCS technique can be extended further by employing a commutated feedback-capacitor switching (CFCS) technique. The prototype ADC achieves better than 53-dB signal-to-noise-and-distortion ratio (SNDR) at 120 MSample/s and 54-dB SNDR and 68-dB spurious-free dynamic range (SFDR) for input frequencies up to Nyquist at 100 MSample/s. The measured differential and integral nonlinearities of the prototype are within /spl plusmn/0.40 LSB and /spl plusmn/0.48 LSB, respectively. The ADC fabricated in a 0.25-/spl mu/m CMOS occupies 3.6 mm/sup 2/ of active die area and consumes 208 mW under a 2.5-V power supply.