• DocumentCode
    987144
  • Title

    A Novel Orthogonal Gate EDMOS Transistor With Improved dv/dt Capability and Figure of Merit (FOM)

  • Author

    Wang, Hao ; Xu, H. P Edward ; Ng, Wai Tung ; Fukumoto, Kenji ; Abe, Ken ; Ishikawa, Akira ; Furukawa, Yuichi ; Imai, Hisaya ; Naito, Takashi ; Sato, Nobuyuki ; Sakai, Kimio ; Tamura, Satoru ; Takasuka, Kaoru

  • Author_Institution
    Dept. of Mater. Sci. & Eng., Toronto Univ., Toronto, ON
  • Volume
    29
  • Issue
    12
  • fYear
    2008
  • Firstpage
    1386
  • Lastpage
    1388
  • Abstract
    A transistor with an orthogonal gate (OG) electrode is proposed to improve dv/dt capability, reduce the gate-to-drain overlap capacitance (C gd), and improve figure of merit (FOM). The OG has both a horizontal section and a vertical section for MOS gate control. This 30-V device is implemented in a 0.18-mum CMOS-compatible process. Comparing to a conventional extended drain MOSFET transistor with the same voltage rating and device size, four times higher dv/dt capability and 53% improvement in FOM are observed.
  • Keywords
    CMOS integrated circuits; MOSFET; CMOS compatible process; MOS gate control; MOSFET transistor; figure of merit; improved dv-dt capability; orthogonal gate EDMOS transistor; orthogonal gate electrode; size 0.18 mum; voltage 30 V; Annealing; CMOS process; CMOS technology; Capacitance; Electrodes; Etching; Fabrication; Lithography; MOSFET circuits; Power MOSFET; $dv/dt$ capability; extended drain MOSFETs (EDMOS); figure of merit (FOM); gate-to-drain capacitance; orthogonal gate (OG);
  • fLanguage
    English
  • Journal_Title
    Electron Device Letters, IEEE
  • Publisher
    ieee
  • ISSN
    0741-3106
  • Type

    jour

  • DOI
    10.1109/LED.2008.2007225
  • Filename
    4671144
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=987144