• DocumentCode
    990486
  • Title

    GAARP: a power-aware GALS architecture for real-time algorithm-specific tasks

  • Author

    Bhunia, Swarup ; Datta, Animesh ; Banerjee, Nilanjan ; Roy, Kaushik

  • Author_Institution
    Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
  • Volume
    54
  • Issue
    6
  • fYear
    2005
  • fDate
    6/1/2005 12:00:00 AM
  • Firstpage
    752
  • Lastpage
    766
  • Abstract
    Reducing the energy consumption of a real-time system has emerged as an important design concern. In this paper, we propose GAARP, an adaptive scalable architecture targeted toward algorithm-specific tasks for just-in-time performance using the right amount of power. The architecture consists of Globally Asynchronous and Locally Synchronous (GALS) building blocks, where the processing hardware is realized by a set of smaller slices of similar structure, each running synchronously with independent clocks. We demonstrate that, for different real-time commercial applications with algorithm-specific jobs like online transaction processing, digital filtering, Fourier transform, etc., the proposed architecture allows dynamic load-balancing and adaptive intertask voltage scaling based on the load in each of the processing units. Compared to a synchronous implementation of the same functionality, we show that the proposed hardware can achieve higher efficiency in terms of power and performance by exploiting the flexibility to balance the load and change the supply voltage. The architecture also lends itself to process tolerance since it can detect process-shifts for the individual processing units and determine the appropriate operating voltage/frequency for each unit. Simulation results for two representative applications show that, for a modest system configuration and random job distribution, we obtain up to 67 percent improvement in MOPS/W (millions of operations per second per watt) over a fully synchronous implementation.
  • Keywords
    computer architecture; energy conservation; fault tolerance; real-time systems; adaptive intertask voltage scaling; adaptive scalable architecture; algorithm-specific tasks; asynchronous-synchronous operation; dynamic load balancing; fault tolerance; power-aware GALS architecture; real-time system; Adaptive filters; Clocks; Digital filters; Dynamic voltage scaling; Energy consumption; Filtering algorithms; Fourier transforms; Frequency; Hardware; Real time systems; Asynchronous/synchronous operations; algorithms implemented in hardware; energy-aware systems.; fault tolerance;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/TC.2005.99
  • Filename
    1461362