Title :
Energy-efficient dual-port cache architecture with improved performances
Author :
Chen, X. ; Bajwa, H.
Author_Institution :
EE Dept., City Coll. of the City Univ. of New York, Grove Sch. Of Eng., NY
Abstract :
Low leakage current and area-efficient dual-port cache design, which uses isolation nodes and local sense amplifiers to facilitate dual-port accesses without duplicating the bit lines for the second port, is presented. Compared with conventional hardwired dual-port cache designs, the average bit line leakage current can be reduced by 50%
Keywords :
cache storage; leakage currents; low-power electronics; memory architecture; dual port cache; energy efficiency; isolation nodes; leakage current;
Journal_Title :
Electronics Letters
