Title :
Source/Drain Extension Region Engineering in FinFETs for Low-Voltage Analog Applications
Author :
Kranti, Abhinav ; Armstrong, G. Alastair
Author_Institution :
Sch. of Electr. & Electron. Eng., Queen´´s Univ., Belfast
Abstract :
In this letter, we propose a novel design methodology for engineering source/drain extension (SDE) regions to simultaneously improve intrinsic dc gain (AVO) and cutoff frequency (fT ) of 25-nm gate-length FinFETs operated at low drain-current (I ds=10 muA/mum). SDE region optimization in 25-nm FinFETs results in exceptionally high values of AVO (~45 dB) and f T (~70 GHz), which is nearly 2.5 times greater when compared to devices designed with abrupt SDE regions. The influence of spacer width, lateral source/drain doping gradient, and the spacer-to-gradient ratio on key analog figures of merit is examined in detail. This letter provides new opportunities for realizing future low-voltage/low-power analog design with nanoscale SDE-engineered FinFETs
Keywords :
MOS analogue integrated circuits; MOSFET circuits; integrated circuit design; low-power electronics; 25 nm; FinFET; gate capacitances; intrinsic voltage gain; low voltage analog applications; region engineering; source/drain extension; spacer-to-gradient ratio; transconductance-to-current ratio; Analytical models; CMOS technology; Cutoff frequency; Design optimization; Doping; FinFETs; Integrated circuit technology; Intrusion detection; Silicon on insulator technology; Voltage; Cutoff frequency; FinFETs; early voltage; gate capacitances; intrinsic voltage gain; low-voltage/low-power analog applications; source/drain extension (SDE) region engineering; transconductance-to-current ratio;
Journal_Title :
Electron Device Letters, IEEE
DOI :
10.1109/LED.2006.889239
