OPASYN: a compiler for CMOS operational amplifiers

Author

Koh, Han Young ; Séquin, Carlo H. ; Gray, Paul R.

Author_Institution

California Univ., Berkeley, CA, USA

Volume

9

Issue

2

fYear

1990

fDate

2/1/1990 12:00:00 AM

Firstpage

113

Lastpage

125

Abstract

A silicon compilation system for CMOS operational amplifiers (OPASYN) is discussed. The synthesis system takes as inputs system-level specifications, fabrication-dependent technology parameters, and geometric layout rules. It produces a design-rule-correct compact layout of an optimized operational amplifier. The synthesis proceeds in three stages: (1) heuristic selection of a suitable circuit topology; (2) parametric circuit optimization based on analytic models; and (3) mask geometry construction using a macro cell layout style. The synthesis process is fast enough for the program to be used interactively at the system design level by system designers who are inexperienced in operational amplifier design

Keywords

CMOS integrated circuits; circuit layout CAD; linear integrated circuits; operational amplifiers; CAD; CMOS operational amplifiers; OPASYN; analytic models; circuit topology; computer aided design; design-rule-correct compact layout; fabrication-dependent technology parameters; geometric layout rules; heuristic selection; macro cell layout style; mask geometry construction; op amp design; parametric circuit optimization; silicon compilation system; synthesis system; system-level specifications; Application software; CMOS technology; Circuit synthesis; Design automation; Design optimization; Filters; Geometry; Operational amplifiers; Silicon; Software libraries;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/43.46777

Filename

46777