A new device architecture suitable for high-resolution and high-performance image sensors

A device architecture for building high-performance and high-resolution image sensors suitable for consumer TV camera applications is introduced. The sensor elements are junction field-effect transistors that are organized in an array with their gates floating and capacitively coupled to common horizontal address line. The photogenerated signal is sampled one line at a time, processed to remove the element-to-element nonuniformities, and stored in a buffer for subsequent readout. The concept, which includes an intrinsic exposure control, is demonstrated on a test image sensor that has an 8-mm sensing area diagonal and 580 (H)×488 (V) pixels. The key performance parameters, in addition to a high packing density of sensing elements with a unique hexagonal shape, include high signal uniformity, low dark current, good light sensitivity, high blooming overload protection, and no image smear. The discussion covers the design and operation of the basic image-sensing element, the architecture of the array, and the operation of the on-chip circuits needed for addressing and processing of generated signals. The overall device performance is demonstrated by typical device characterization results