• DocumentCode
    994502
  • Title

    Efficient via shifting algorithms in channel compaction

  • Author

    Cai, Yang ; Wong, D.F.

  • Author_Institution
    ArcSys Inc., Sunnyvale, CA, USA
  • Volume
    12
  • Issue
    12
  • fYear
    1993
  • fDate
    12/1/1993 12:00:00 AM
  • Firstpage
    1848
  • Lastpage
    1857
  • Abstract
    Considers in this paper the problem of shifting vias to obtain more compactable channel routing solutions. Let S be a grid-based two-layer channel routing solution. Let vc, wc be the number of grid points on column c that are occupied by vias, horizontal wires in S, respectively. The authors define the expected height of columns c in S to be hc=Avc+Bwc +C, where A, B, C are some design rule dependent constants. A column in S is said to be a critical column if it has maximum expected height among all columns in S. Let HS=maxchc be the expected height of the critical column(s) of S. HS is an estimation of the height of S after compaction. The authors show that the problem of shifting vias to minimize HS can be solved optimally in polynomial time
  • Keywords
    VLSI; circuit layout CAD; network routing; wiring; VLSI; channel compaction; channel routing solutions; critical column; design rule dependent constants; grid points; grid-based two-layer channel routing; horizontal wires; maximum expected height; polynomial time; via shifting algorithms; Circuits and systems; Compaction; Design automation; Helium; Polynomials; Routing; Scholarships; Tree graphs; Very large scale integration; Wires;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/43.251148
  • Filename
    251148