Analytical and simulation studies of failure modes in SRAMs using high electron mobility transistors

Gallium arsenide memories, which are now beginning to be used commercially, are subject to certain unusual parametric faults, not normally seen in silicon or other memory devices. This paper studies the behavior of gallium arsenide high electron mobility transistor (HEMT) memories in the presence of material defects, processing errors and design errors to formulate efficient testing schemes. All defects and errors are mapped into equivalent circuit modifications and the resulting circuits are analyzed and simulated to observe the fault effects. Certain complex pattern-sensitive faults described in the testing literature are not observed at all, while certain other faults which have not been previously studied, are observed. It is shown that by slightly modifying and reordering existing test procedures, all faults in these RAMs can be tested