High-performance self-aligned p+/n GaAs epitaxial JFET´s incorporating AlGaAs etch-stop layer

The fabrication of high-transconductance epitaxial GaAs JFETs using a refractory metal self-aligned gate (SAG) process is discussed. By applying a highly doped, shallow epitaxial channel (n≈1×10¹⁸ cm^-3), a T-gate structure consisting of WSi or WN/p⁺ GaAs, and a thin undoped AlGaAs etch-stop layer (75 Å) separating the p⁺ GaAs and the active JFET n-channel, high-performance devices which show GaAs JFETs to be applicable to ultra-high-speed circuits have been realized. 1-, 0.85-, and 0.6-μm gate length devices of 10-μm gate width and threshold voltages near 0.3 V exhibited transconductances of 354, 406, and 440 mS/mm, respectively, at V_gs=1 V and V _ds of 1.5 V. The 0.6×10-μm device exhibited a peak transconductance of 554 mS/mm at V_gs=1.3 V and a K value of 352 μA/V²-μm. The peak transconductance occurs at a gate-to-source voltage below the bipolar regime of conduction of the FETs