DocumentCode
995461
Title
SoC yield optimization via an embedded-memory test and repair infrastructure
Author
Shoukourian, Samvel ; Vardanian, Valery ; Zorian, Yervant
Author_Institution
Virage Logic, Fremont, CA, USA
Volume
21
Issue
3
fYear
2004
Firstpage
200
Lastpage
207
Abstract
Today, embedded memories are the most important contributor to SoC yield. To maximize embedded-memory yield, advanced test and repair solutions must be an integral part of the memory block. We analyze factors that affect memory yield and presents advanced techniques for maximizing the positive impact.
Keywords
built-in self test; integrated circuit testing; integrated circuit yield; logic testing; system-on-chip; SoC yield optimization; built-in self test; embedded memory testing; integrated circuit testing; integrated circuit yield; logic testing; system-on-chip; Algorithm design and analysis; Fault detection; Fault diagnosis; Fault location; Fuses; History; Logic; Performance analysis; Redundancy; Testing;
fLanguage
English
Journal_Title
Design & Test of Computers, IEEE
Publisher
ieee
ISSN
0740-7475
Type
jour
DOI
10.1109/MDT.2004.19
Filename
1302086
Link To Document