Title :
Risk Reduction for Use of Complex Devices in Space Projects
Author :
Berg, M. ; Poivey, C. ; Petrick, D. ; LaBel, K. ; Friendlich, M. ; Stansberry, S. ; Kim, H.
Author_Institution :
NASA/GSFC, MEI Technol., Inc., Greenbelt, MD
Abstract :
We present guidelines to reduce risk to an acceptable level when using complex devices in space applications. An example of application for the use of Virtex 4 field programmable gate array (FPGA) on express logistic carrier(ELC) project is presented.
Keywords :
field programmable gate arrays; risk analysis; system-on-chip; ELC; Express Logistic Carrier project; FPGA; International Space Station; Virtex 4 Field Programmable Gate Array; complex System-On-Chip device; external hardened scrubber; risk reduction; Circuit faults; Circuit testing; Field programmable gate arrays; Logistics; NASA; Risk management; Single event upset; Space technology; State-space methods; System-on-a-chip; FPGA; Xilinx; risk reduction; scrubbing;
Journal_Title :
Nuclear Science, IEEE Transactions on
DOI :
10.1109/TNS.2007.910291
