Title :
A 3.3 V 6 bits 60 MHz CMOS dual ADC
Author :
Paillardet, F. ; Robert, P.
Author_Institution :
Thomson Consumer Electron. Components, Meylan, France
fDate :
8/1/1995 12:00:00 AM
Abstract :
The paper describes a 6 bit dual A/D with a 60 MHz conversion rate in a 3.3 V 0.5 μm CMOS process. It uses autozeroed comparators combined with interpolation and offset cancellation techniques
Keywords :
CMOS integrated circuits; analogue-digital conversion; interpolation; 0.5 micron; 3.3 V; 3.3 V 6 bits 60 MHz CMOS dual ADC; 6 bit; 60 MHz; autozeroed comparators; conversion rate; interpolation; offset cancellation; Analog-digital conversion; CMOS process; CMOS technology; Clocks; Consumer electronics; Digital TV; Energy consumption; Interpolation; Satellite broadcasting; Switches;
Journal_Title :
Consumer Electronics, IEEE Transactions on
