Title :
Ion implantation of neon in silicon for planar amorphous isolation
Author_Institution :
Massachusetts Institute of Technology, Lincoln Laboratory, Lexington, USA
Abstract :
A new planar isolation technique for silicon integrated circuits is presented. The process uses neon implantation to create high-resistivity regions of amorphous silicon between active devices on a common substrate. Excellent surface planarity is obtained, and no high-temperature processing ii required. Results on test devices and an amorphous isolated m.n.o.s. capacitor memory are described.
Keywords :
integrated circuit technology; ion implantation; monolithic integrated circuits; MNOS capacitor memory; Ne ion implantation; Si; integrated circuits; monolithic integrated circuits; planar amorphous isolation; planar isolation technique; surface planarity;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19780310
