Title :
Low-Power, High-Speed Transceivers for Network-on-Chip Communication
Author :
Schinkel, Daniël ; Mensink, Eisse ; Klumperink, Eric A M ; Van Tuijl, Ed ; Nauta, Bram
Author_Institution :
Axiom-IC B.V, Enschede
Abstract :
Networks on chips (NoCs) are becoming popular as they provide a solution for the interconnection problems on large integrated circuits (ICs). But even in a NoC, link-power can become unacceptably high and data rates are limited when conventional data transceivers are used. In this paper, we present a low-power, high-speed source-synchronous link transceiver which enables a factor 3.3 reduction in link power together with an 80% increase in data-rate. A low-swing capacitive pre-emphasis transmitter in combination with a double-tail sense-amplifier enable speeds in excess of 9 Gb/s over a 2 mm twisted differential interconnect, while consuming only 130 fJ/transition without the need for an additional supply. Multiple transceivers can be connected back-to-back to create a source-synchronous transceiver-chain with a wave-pipelined clock, operating with 6sigma offset reliability at 5 Gb/s.
Keywords :
high-speed integrated circuits; integrated circuit interconnections; large scale integration; low-power electronics; network-on-chip; transceivers; NoC; bit rate 5 Gbit/s; double-tail sense-amplifier; high-speed source-synchronous link transceiver; integrated circuit interconnection; large integrated circuits; low-swing capacitive pre-emphasis transmitter; network-on-chip communication; size 2 mm; twisted differential interconnect; wave-pipelined clock; Capacitive pre-emphasis transmitter; globally asynchronous, locally synchronous (GALS); interconnect; low-power design; low-swing; network on chip (NoC); on-chip communication; source synchronous; wave-pipelining;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
DOI :
10.1109/TVLSI.2008.2001949
