Offset word-line architecture for scaling DRAMs to the gigabit level

An alternative to the boosted word-line DRAM architecture is described that is scalable to the gigabit level and avoids the problems of poor performance and high gate fields of conventional boosted word-line circuits. The alternative is called an offset word-line architecture, because the cell switch is changed to depletion mode and the word line is pulled beyond the cell switch device´s source voltage rather than boosted beyond its drain voltage. The large voltage swing for the word line does not cause large fields across the gate dielectric in the word-line driver or array access device because the gates of some devices use materials with modified work functions. The word-line voltage swing can be greater than the bit-line voltage swing plus the required threshold voltage even for gigabit-scale integration DRAM technologies.<>