ﻃﺮاﺣﯽ ﯾﮏ ﮔﯿﺖ اﮐﺜﺮﯾﺖ ﭘﻨﺞ ورودي ﺗﺤﻤﻞ ﭘﺬﯾﺮ اﺷﮑﺎل در اﺗﻮﻣﺎﺗﺎي ﺳﻠﻮﻟﯽ ﮐﻮاﻧﺘﻮﻣﯽ

A Defect Tolerant Design for 5-Input Majority Gate in Quantum-dot Cellular Automata

ﭼﮑﯿﺪه: اﺗﻮﻣﺎﺗﺎي ﺳﻠﻮﻟﯽ ﮐﻮاﻧﺘﻮﻣﯽ ﯾﮏ ﺗﮑﻨﻮﻟﻮژي ﺟﺪﯾﺪ ﺟﻬﺖ ﭘﯿﺎده ﺳﺎزي ﮔﯿﺖ ﻫﺎي ﻣﻨﻄﻘﯽ و ﻣﺪارﻫﺎي دﯾﺠﯿﺘﺎل در ﻣﻘﯿﺎس ﻧﺎﻧﻮ اﺳﺖ. ﺑﺎ ﮐﺎﻫﺶ اﺑﻌﺎد ﻗﻄﻌﺎت، ﺣﺴﺎﺳﯿﺖ ﻣﺪار ﺑﯿﺸﺘﺮ ﺷﺪه و ﻣﺪارﻫﺎي ﮐﻮاﻧﺘﻮﻣﯽ ﻧﺴﺒﺖ ﺑﻪ ﻋﻮاﻣﻞ ﻧﺎﻣﺴﺎﻋﺪ ﻣﺤﯿﻂ آﺳﯿﺐ ﭘﺬﯾﺮﺗﺮ ﻫﺴﺘﻨﺪ. ﺑﺎ ﺗﻮﺟﻪ ﺑﻪ اﻫﻤﯿﺖ ﻃﺮاﺣﯽ ﻣﺪارات ﺗﺤﻤﻞ ﭘﺬﯾﺮ اﺷﮑﺎل، در اﯾﻦ ﻣﻘﺎﻟﻪ ﺑﻪ اراﺋﻪ ﯾﮏ ﮔﯿﺖ اﮐﺜﺮﯾﺖ ﭘﻨﺞ ورودي ﺑﺎ وﯾﮋﮔﯽ ﺗﺤﻤﻞ ﭘﺬﯾﺮي اﺷﮑﺎل در ﺗﮑﻨﻮﻟﻮژي اﺗﻮﻣﺎﺗﺎي ﺳﻠﻮﻟﯽ ﮐﻮاﻧﺘﻮﻣﯽ ﻣﯽ ﭘﺮدازﯾﻢ و ﺗﻤﺎم اﺷﮑﺎل ﻫﺎي ﻣﻤﮑﻦ در ﭘﺮوﺳﻪ ﺟﺎﯾﮕﺬاري ﺳﻠﻮل ﻫﺎ در ﻣﮑﺎن ﻫﺎي ﺧﺎﺻﯽ در روي ﺳﻄﺢ را ﻣﻮرد ارزﯾﺎﺑﯽ ﻗﺮار ﻣﯽ دﻫﯿﻢ. اﯾﻦ اﺷﮑﺎل ﻫﺎ ﺷﺎﻣﻞ ﺟﺎﺑﺠﺎﯾﯽ، ﺣﺬف، ﭼﺮﺧﺶ و ﺳﻠﻮل اﺿﺎﻓﻪ ﻣﯽ ﺑﺎﺷﻨﺪ. در ﮔﺎم ﻧﺨﺴﺖ ﺑﻪ ﮔﯿﺖ ﻣﻮرد ﺑﺮرﺳﯽ ﭼﻬﺎر ﻧﻮع اﺷﮑﺎل ذﮐﺮ ﺷﺪه اﻋﻤﺎل ﮔﺮدﯾﺪه و در ﮔﺎم ﺑﻌﺪي ﺻﺤﺖ ﻋﻤﻠﮑﺮد ﻣﺪار ﺑﺎ ﻣﻮﺗﻮر ﺷﺒﯿﻪ ﺳﺎز QCADesigner ﻣﻮرد ارزﯾﺎﺑﯽ ﻗﺮار داده ﻣﯽ ﺷﻮد . ﺑﺮاي ﯾﺎﻓﺘﻦ ﭼﻨﯿﻦ ﮔﯿﺖ اﮐﺜﺮﯾﺘﯽ روش ﻫﺎي ﻣﺨﺘﻠﻔﯽ از ﺟﻤﻠﻪ روش اﻓﺰودن ﺳﻠﻮل )ﮐﻪ ﻫﻤﺎن ﺗﺰرﯾﻖ اﻓﺰوﻧﮕﯽ ﺑﻪ ﻣﺪار اﺳﺖ( و روش ﭼﯿﻨﺶ ﺧﺎص ﺳﻠﻮل ﻫﺎ ﻣﻮرد آزﻣﺎﯾﺶ ﻗﺮار ﻣﯽ ﮔﯿﺮد. ﺳﻌﯽ ﺑﺮ اﯾﻦ اﺳﺖ ﮐﻪ ﻃﺮﺣﯽ ﯾﺎﻓﺖ ﺷﻮد ﮐﻪ ﺣﺘﯽ اﻻﻣﮑﺎن ﺗﻨﻬﺎ ﺑﺎﭼﯿﻨﺶ ﺧﺎص ﺳﻠﻮل ﻫﺎ ﺗﻮاﻧﺎﯾﯽ ﻣﻘﺎوﻣﺖ در ﺑﺮاﺑﺮ ﻧﻘﺺ ﻫﺎي اﺣﺘﻤﺎﻟﯽ را داﺷﺘﻪ ﺑﺎﺷﺪ ﺑﻪ ﮔﻮﻧﻪ اي ﮐﻪ ﺣﺪاﻗﻞ ﺳﺮﺑﺎر ﺑﻪ ﻣﺪار ﺟﻬﺖ ﺗﺤﻤﻞ ﭘﺬﯾﺮي اﺷﮑﺎل ﺗﺤﻤﯿﻞ ﺷﻮد . ﻧﺘﺎﯾﺞ ﻧﺸﺎن ﻣﯽ دﻫﺪ ﮐﻪ ﮔﯿﺖ اﮐﺜﺮﯾﺖ ﻣﻌﺮﻓﯽ ﺷﺪه در ﻣﻘﺎﯾﺴﻪ ﺑﺎ ﻣﻮارد ﻣﺸﺎﺑﻪ از ﺑﺮﺗﺮي ﻗﺎﺑﻞ ﺗﻮﺟﻬﯽ ﺑﺮﺧﻮردار اﺳﺖ.

Quantum-dot cellular automaton is a new technology for implementation of logic gates and digital circuits at nanoscale. By reducing size of the components, sensitivity of circuit increases and quantum circuits become more vulnerable to adverse environmental factors. Due to the importance of designing fault tolerant circuits, this paper presents a five-input majority gate with fault tolerance characteristic in quantum cellular automata technology. All possible faults which may occur during the process of placing cells in specific locations on the surface including displacement, deletion, rotation, and extra cell are evaluated. In the first step, all the four types of faults are applied to the gate and the next step is to evaluate the accuracy of the gate performance with the QCADesigner simulator. In order to find such a majority gate, different methods, including the method of adding cells (the injection of redundancy to the gate) and the specific arrangement of cells are utilized. The latter method is being used more, hence, low overhead is added to the design. The results confirm the superiority of the proposed gate over the other previously offered designs.